The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a vertical channel transistor.
As semiconductor devices have become highly integrated, methods for fabricating semiconductor devices have reached the limitation in many aspects. When a channel length decreases, the semiconductor devices can be highly integrated. However, short channel effects such as a drain induces barrier lowering, a hot carrier effect, and a punch through are caused.
To prevent the short channel effect, various methods for increasing the channel length, e.g., etch of the silicon in a channel region, are introduced.
However, as an integration density of a semiconductor memory device, particularly, a Dynamic Random Access Memory (DRAM), approaches giga bits, fabrication of a smaller transistor is required. In other words, gigabit-class DRAM transistors require a device dimension under 4F2 (where F is a minimum feature size) or less. Therefore, an existing planar MOS transistor structure having a gate electrode over a substrate and junction regions on both sides of the gate electrode hardly satisfy a required device dimension even though the channel length is scaled.
To overcome the above limitations, a vertical channel transistor has been introduced.
FIGS. 1A to 1C are cross-sectional views illustrating a method for fabricating a typical vertical channel transistor.
Referring to FIG. 1A, a substrate 11 is etched to a certain depth using a hard mask pattern 12 as an etch barrier. Thus, a first pillar 13 is formed. A capping layer 14 is formed on sidewalls of the first pillar 13. The substrate 11 under the first pillar 13 is etched more using the hard mask pattern 12 as an etch barrier. Thus, a second pillar 15 is formed.
Referring to FIG. 1B, an isotropic dry etch process is performed on sidewalls of the second pillar 15. Thus, a second pillar pattern 15A is formed.
Referring to FIG. 1C, a gate insulation layer 16 is formed over a surface of the second pillar pattern 15A and substrate 11. A gate electrode 17 surrounding external walls of the second pillar pattern 15A is formed. Material for the gate electrode may include polysilicon.
FIGS. 2A and 2B illustrate a method for fabricating a typical gate electrode 17.
Referring to FIG. 2A, polysilicon 17 is deposited in a resultant structure including the second pillar pattern 15A. The resultant structure including the second pillar pattern 15A has a narrow opening and a wide bottom. Thus, a seam 22 is generated during the deposition of the polysilicon 17.
Referring to FIG. 2B, an isotropic etch process is performed on the polysilicon 17 including the seam 22. Thus, the polysilicon 17 remains on sidewalls of the second pillar pattern 15A.
Since the seam 22 is generated when the polysilicon 17 is deposited, a gate oxide layer 16 and the substrate below the seam 22 may be attacked when the polysilicon 17 is etched. Thus, a punch 24 may be generated.
The punch 24 may cause a deposition uniformity defect when an insulation layer is deposited during a formation of a Buried Bit Line (BBL), or etch residuals from the punch 24 may function as an etch barrier when the BBL is etched.